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1996, 2000 data sheet mos integrated circuit m pd78f4046 16-bit single-chip microcontroller description the m pd78f4046 is a product of the m pd784046 subseries in the 78k/iv series. the m pd78f4046 has flash memory in place of the internal rom of the m pd784046. the incorporation of flash memory allows a program to be written or erased while mounted on the target board. detailed function descriptions are provided in the following users manuals. be sure to read them before designing. m pd784046 subseries users manual hardware: u11515e 78k/iv series users manual instruction: u10905e features ? 78k/iv series ? pin compatible with m pd784044, 784046 (except v pp pin) ? flash memory: 64 kb ? internal ram: 2048 bytes ? operable with the same supply voltage as that of the mask rom version: v dd = 4.5 to 5.5 v applications ? water heaters, vending machines, etc. ? fa fields such as robots, automated machine tools, etc. ordering information part number package m pd78f4046gc-3b9 80-pin plastic qfp (14 14 mm) the mark shows major revised points. document no. u11447ej2v0ds00 (2nd edition) date published august 2000 n cp(k) printed in japan the information in this document is subject to change without notice. before using this document, please confirm that this is the latest version. not all devices/types available in every country. please check with local nec representative for availability and additional information.
m pd78f4046 2 data sheet u11447ej2v0ds00 78k/iv series lineup assp models standard models enhanced a/d, 16-bit timer, power management m pd784026 m pd784038y m pd784054 m m pd784046 m pd784038 m pd784216/ m pd784225y m pd784218y/ m pd784956a m pd784938a m pd784908 m pd784976a m pd784915 m pd784928y i 2 c bus supported multimaster i 2 c bus supported on-chip 10-bit a/d multimaster i 2 c bus supported 80 pins, rom correction added multimaster i 2 c bus supported expanded internal memory capacity, rom correction added for dc inverter control on-chip iebus tm controller on-chip vfd controller/driver software servo control, on-chip analog circuit for vcr, enhanced timer multimaster i 2 c bus supplied pd784908 with enhanced functions, expanded internal memory capacity, rom correction added pd784915 with enhanced functions expanded internal memory capacity, pin compatible with pd784026 m 100 pins, enhanced i/o, expanded internal memory capacity : products in mass production : products under development m pd784225 m pd784218/ m pd784218a m pd784928 m pd784216y/ m pd784216ay m pd784216a m pd784218ay m enhanced functions of the pd784938a, enhanced i/o and internal memory capacity m pd784967 m
m pd78f4046 3 data sheet u11447ej2v0ds00 overview of functions item function number of basic 113 instructions (mnemonics) general-purpose registers 8 bits 16 registers 8 banks, or 16 bits 8 registers 8 banks (memory mapping) minimum instruction 125 ns (@16 mhz operation with internal clock) execution time internal flash memory 64 kb memory ram 2048 bytes memory space 1 mb with program/data combined i/o ports total 65 input 17 i/o 48 pins with pins with 29 ancillary pull-up functions note resistors real-time output port 4 bits 1 timers timer 0: timer counter 1 pulse output (16 bits) capture/compare register 4 ? toggle output ? set/reset output timer 1: timer counter 1 pulse output (16 bits) compare register 2 ? toggle output ? set/reset output timer/event counter 2: timer counter 1 pulse output (16 bits) compare register 2 ? toggle output ? pwm/ppg output timer/event counter 3: timer counter 1 pulse output (16 bits) compare register 2 ? toggle output ? pwm/ppg output timer 4: timer counter 1 pulse output (16 bits) compare register 2 ? real-time output (4 bits 1) a/d converter 10-bit resolution 16 channels serial interface uart/ioe (3-wire serial i/o): 2 channels (with baud rate generator) watchdog timer 1 channel interrupts sources 27 (internal: 23, external: 8 (internal/external: 4)) + brk instruction software brk instruction non-maskable internal: 1, external: 1 maskable internal: 22, external: 7 (internal/external: 4) ? 4 programmable priority levels ? 3 service modes: vectored interrupt/macro service/context switching bus sizing 8-bit/16-bit external data bus width selectable standby halt/stop/idle modes supply voltage v dd = 4.5 to 5.5 v package 80-pin plastic qfp (14 14 mm) note the pins with ancillary functions are included in the i/o pins.
m pd78f4046 4 data sheet u11447ej2v0ds00 contents 1. differences among m pd784046 subseries ........................................................................... 5 2. pin configuration (top view) ................................................................................................... 6 3. system configuration example (ac servo motor control) .................................... 8 4. block diagram ............................................................................................................................... 9 5. pin functions ............................................................................................................................... .10 5.1 port pins ............................................................................................................................... ..................... 10 5.2 non-port pins ............................................................................................................................... ............. 12 5.3 pin i/o circuits and recommended connection of unused pins ..................................................... 14 6. internal memory size switching register (ims) ........................................................... 16 7. flash memory programming ................................................................................................. 17 7.1 selecting communication mode ............................................................................................................ 17 7.2 function of flash memory programming ............................................................................................. 18 7.3 connection of flashpro ii and flashpro iii ........................................................................................... 18 7.4 cautions when writing to flash memory ............................................................................................. 19 8. electrical specifications ...................................................................................................... 21 9. package drawing ........................................................................................................................32 10. recommended soldering conditions ............................................................................... 33 appendix a. development tools ................................................................................................34 appendix b. related documents ............................................................................................... 37
m pd78f4046 5 data sheet u11447ej2v0ds00 1. differences among m pd784046 subseries the only difference between the m pd784044 and m pd784046 is the internal memory capacity. the m pd78f4046 is a version of the m pd784046 with the internal rom replaced by flash memory. the differences are shown in table 1-1. table 1-1. differences among m pd784046 subseries part number m pd784044 m pd784046 m pd78f4046 item internal rom 32 kb 64 kb 64 kb (mask rom) (mask rom) (flash memory) internal ram 1024 bytes 2048 bytes function of pin 57 mode mode/v pp
m pd78f4046 6 data sheet u11447ej2v0ds00 2. pin configuration (top view) ? 80-pin plastic qfp (14 14 mm) m pd78f4046gc-3b9 caution connect the mode/v pp pin directly to v ss in normal operation mode. p70/ani0 p71/ani1 p72/ani2 p73/ani3 p74/ani4 p75/ani5 p76/ani6 p77/ani7 av ref av dd v ss v dd p47/ad7 p46/ad6 p45/ad5 p44/ad4 p43/ad3 p42/ad2 p41/ad1 p40/ad0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 p22/intp1/to01 bwd p21/intp0/to00 mode/v pp p20/nmi v ss v dd p13/to31 p12/to30 p11/to21 p10/to20 p03/rtp3 p02/rtp2 p01/rtp1 p00/rtp0 p37/asck2/sck2 p36/txd2/so2 p35/rxd2/si2 p34/asck/sck1 p33/txd/so1 p50/ad8 p51/ad9 p52/ad10 p53/ad11 p54/ad12 p55/ad13 p56/ad14 p57/ad15 p60/a16 p61/a17 p62/a18 p63/a19 p90/rd p91/lwr p92/hwr p93/astb p94/wait p30/to10 p31/to11 p32/rxd/si1 p87/ani15 p86/ani14 p85/ani13 p84/ani12 p83/ani11 p82/ani10 p81/ani9 p80/ani8 av ss v dd x2 x1 v ss clkout p27/intp6/ti3 p26/intp5/ti2 p25/intp4 p24/intp3/to03 reset p23/intp2/to02 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
m pd78f4046 7 data sheet u11447ej2v0ds00 p00 to p03: port 0 p10 to p13: port 1 p20 to p27: port 2 p30 to p37: port 3 p40 to p47: port 4 p50 to p57: port 5 p60 to p63: port 6 p70 to p77: port 7 p80 to p87: port 8 p90 to p94: port 9 rtp0 to rtp3: real-time port nmi: nonmaskable interrupt intp0 to intp6: interrupt from peripherals to00 to to03, to10, to11: timer output to20, to21, to30, to31 : ti2, ti3: timer input rxd, rxd2: receive data txd, txd2: transmit data asck, asck2: asynchronous serial clock si1, si2,: serial input so1, so2: serial output sck1, sck2: serial clock ad0 to ad15: address/data bus a16 to a19: address bus rd: read strobe lwr: low address write strobe hwr: high address write strobe astb: address strobe wait: wait bwd: bus width definition mode: mode clkout: clock out x1, x2: crystal reset: reset ani0 to ani15: analog input av ref : analog reference voltage av dd : analog power supply av ss : analog ground v dd : power supply v pp : programming power supply v ss : ground
m pd78f4046 8 data sheet u11447ej2v0ds00 3. system configuration example (ac servo motor control) uart 3-wire serial i/o wdt pd78f4046 control panel display keypad i/o port external tester i/o interface circuit cpu-to-cpu communication flash memory 64 kb ram 2048 bytes macro service function port intp0 to intp4 ani8 to ani15 to10, to11, to20, to21 port ani0 to ani7 intp5 ad0 to ad15 limit switch driver/switching circuit current/voltage sensor signal input circuit ac motor rotary encoder rotary encoder interface encoder pulse counter m
m pd78f4046 9 data sheet u11447ej2v0ds00 4. block diagram programmable interrupt controller intp0 to intp6 nmi to00 to to03 intp0 to intp3 to10, to11 a/d converter av dd av ss av ref intp4 ani0 to ani15 watchdog timer timer 4 (16 bits) timer 1 (16 bits) timer 0 (16 bits) 78k/iv cpu core flash memory ram bus i/f bwd ad0 to ad15 a16 to a19 rd lwr, hwr astb wait clkout reset mode/v pp x1 x2 system control p00 to p03 port 0 port 1 port 2 port 3 port 4 port 5 port 6 port 7 port 8 port 9 p10 to p13 p20 p21 to p27 v dd v ss p30 to p37 p40 to p47 p50 to p57 p60 to p63 p70 to p77 p80 to p87 p90 to p94 baud rate generator uart/ioe1 baud rate generator uart/ioe2 txd/so1 rxd/si1 asck/sck1 txd2/so2 rxd2/si2 asck2/sck2 timer/event counter 2 (16 bits) to20, to21 intp5/ti2 to30, to31 intp6/ti3 rtp0 to rtp3 real-time output port timer/event counter 3 (16 bits)
m pd78f4046 10 data sheet u11447ej2v0ds00 5. pin functions 5.1 port pins (1/2) pin name i/o alternate function function p00 to p03 i/o rtp0 to rtp3 port 0 (p0): ? 4-bit i/o port ? input/output can be specified in 1-bit units. ? when used as an input port, an on-chip pull-up resistor can be specified by means of software. p10 i/o to20 port 1 (p1): p11 to21 ? 4-bit i/o port p12 to30 ? input/output can be specified in 1-bit units. p13 to31 p20 input nmi port 2 (p2): input only p21 i/o intp0/to00 ? 8-bit i/o port input/output can be specified in p22 intp1/to01 1-bit units. p23 intp2/to02 p24 intp3/to03 p25 intp4 p26 intp5/ti2 p27 intp6/ti3 p30 i/o to10 port 3 (p3): p31 to11 ? 8-bit i/o port p32 rxd/si1 ? input/output can be specified in 1-bit units. p33 txd/so1 p34 asck/sck1 p35 rxd2/si2 p36 txd2/so2 p37 asck2/sck2 p40 to p47 i/o ad0 to ad7 port 4 (p4): ? 8-bit i/o port ? input/output can be specified in 1-bit units. ? when used as an input port, an on-chip pull-up resistor can be specified by means of software. p50 to p57 i/o ad8 to ad15 port 5 (p5): ? 8-bit i/o port ? input/output can be specified in 1-bit units. ? when used as an input port, an on-chip pull-up resistor can be specified by means of software. p60 to p63 i/o a16 to a19 port 6 (p6): ? 4-bit i/o port ? input/output can be specified in 1-bit units. ? when used as an input port, an on-chip pull-up resistor can be specified by means of software.
m pd78f4046 11 data sheet u11447ej2v0ds00 5.1 port pins (2/2) pin name i/o alternate function function p70 to p77 input ani0 to ani7 port 7 (p7): ? 8-bit input-only port p80 to p87 input ani8 to ani15 port 8 (p8): ? 8-bit input-only port p90 i/o rd port 9 (p9): p91 lwr ? 5-bit i/o port p92 hwr ? input/output can be specified in 1-bit units. p93 astb ? when used as an input port, an on-chip pull-up resistor can be p94 wait specified by means of software.
m pd78f4046 12 data sheet u11447ej2v0ds00 5.2 non-port pins (1/2) pin name i/o alternate function function rtp0 to rtp3 output p00 to p03 real-time output nmi input p20 non-maskable interrupt request input intp0 p21/to00 external interrupt capture trigger signal of cc00 intp1 p22/to01 request input capture trigger signal of cc01 intp2 p23/to02 capture trigger signal of cc02 intp3 p24/to03 capture trigger signal of cc03 intp4 p25 conversion start trigger input of a/d converter intp5 p26/ti2 C intp6 p27/ti3 to00 output p21/intp0 timer output from timer to01 p22/intp1 to02 p23/intp2 to03 p24/intp3 to10 p30 to11 p31 to20 p10 to21 p11 to30 p12 to31 p13 ti2 input p26/intp5 external count clock input to timer/event counter 2 ti3 p27/intp6 external count clock input to timer/event counter 3 rxd p32/si1 serial data input (uart0) rxd2 p35/si2 serial data input (uart2) txd output p33/so1 serial data output (uart0) txd2 p36/so2 serial data output (uart2) asck input p34/sck1 baud rate clock input (uart0) asck2 p37/sck2 baud rate clock input (uart2) si1 p32/rxd serial data input (3-wire serial i/o1) si2 p35/rxd2 serial data input (3-wire serial i/o2) so1 output p33/txd serial data output (3-wire serial i/o1) so2 p36/txd2 serial data output (3-wire serial i/o2) sck1 i/o p34/asck serial clock input/output (3-wire serial i/o1) sck2 p37/asck2 serial clock input/output (3-wire serial i/o2) ad0 to ad7 p40 to p47 lower multiplexed address/data bus for expanding memory externally ad8 to ad15 note p50 to p57 ? when 8-bit bus is specified higher address bus for expanding memory externally ? when external 16-bit bus is specified higher multiplexed address/data bus for expanding memory externally a16 to a19 note output p60 to p63 higher address bus for expanding memory externally rd p90 read strobe to external memory note the number of pins used as address bus pins differs depending on the external address space.
m pd78f4046 13 data sheet u11447ej2v0ds00 5.2 non-port pins (2/2) pin name i/o alternate function function lwr output p91 ? when external 8-bit bus is specified write strobe to external memory ? when external 16-bit bus is specified write strobe to external memory located at lower address hwr p92 write strobe to external memory located at higher address when external 16-bit bus is specified astb output p93 timing signal output that externally latches address information output from ad0 through ad15 pins to access external memory wait input p94 wait insertion bwd C bus width setting mode v pp connect directly to v ss in normal operation mode (for specification of ic test mode). clkout output C clock output x1 input C connecting crystal resonator for system clock oscillation x2 C C (clock can be input to x1). reset input C chip reset ani0 to ani7 p70 to p77 analog voltage input for a/d converter ani8 to ani15 p80 to p87 av ref C C reference voltage application for a/d converter av dd C positive power supply for a/d converter av ss C gnd for a/d converter v dd C positive power supply v pp input mode flash memory programming mode setting applying high-voltage for program write/verify. v ss C C gnd
m pd78f4046 14 data sheet u11447ej2v0ds00 5.3 pin i/o circuits and recommended connection of unused pins the input/output circuit type of each pin and recommended connection of unused pins are shown in table 5-1. for the i/o circuit configuration of each type, refer to figure 5-1. table 5-1. types of pin i/o circuits and recommended connection of unused pins pin name i/o circuit type i/o recommended connection of unused pins p00/rtp0 to p03/rtp3 5-a i/o input: independently connect to v dd or v ss via a resistor. p10/to20 5 output: leave open. p11/to21 p12/to30 p13/to31 p20/nmi 2 input connect to v ss . p21/intp0/to00 8 i/o input: independently connect to v dd or v ss via a resistor. p22/intp1/to01 output: leave open. p23/intp2/to02 p24/intp3/to03 p25/intp4 p26/intp5/ti2 p27/intp6/ti3 p30/to10 5 p31/to11 p32/rxd/si1 p33/txd/so1 p34/asck/sck1 8 p35/rxd2/si2 5 p36/txd2/so2 p37/asck2/sck2 8 p40/ad0 to p47/ad7 5-a p50/ad8 to p57/ad15 p60/a16 to p63/a19 p70/ani0 to p77/ani7 9 input connect to v ss . p80/ani8 to p87/ani15 p90/rd 5-a i/o input: independently connect to v dd or v ss via a resistor. p91/lwr output: leave open. p92/hwr p93/astb p94/wait mode 1 input C reset 2 clkout 3 output leave open. av ref C C connect to v ss . av ss av dd connect to v dd . remark since type numbers are standardized among the 78k series products, they are not sequential in some models (i.e., some circuits are not provided).
m pd78f4046 15 data sheet u11447ej2v0ds00 figure 5-1. pin i/o circuits type 2 schmitt-triggered input with hysteresis characteristics type 1 p-ch in v dd n-ch in type 3 type 5 data output disable p-ch in/out v dd n-ch input enable type 5-a data output disable p-ch in/out v dd n-ch input enable p-ch v dd pullup enable type 8 data output disable p-ch in/out v dd n-ch in comparator + v ref (threshold voltage) p-ch n-ch input enable type 9 p-ch out v dd n-ch
m pd78f4046 16 data sheet u11447ej2v0ds00 6. internal memory size switching register (ims) ims is a register that is set by software and is used to specify a part of the internal memory that is not to be used. by setting this register, the internal memory of the m pd78f4046 can be mapped identically to that of a mask rom version with a different internal memory (rom and ram) capacity. ims is set with an 8-bit memory manipulation instruction. reset input sets ims to deh. figure 6-1. internal memory size switching register (ims) format table 6-1 shows the ims setting values to make the memory mapping the same as that of the mask rom versions. table 6-1. setting values of internal memory size switching register (ims) target mask rom version ims setting value m pd784044, 784054 cdh note m pd784046 deh note when ims is set to cdh, the peripheral ram capacity of the m pd78f4046 is 768 bytes, but that of the m pd784044 or 784054 is 512 bytes. consequently, when making a mask rom version, be sure not to use 0fa00h through 0faffh in the peripheral ram area of m pd78f4046 (upon the execution of the location 0h instruc- tion). 7 1 6 1 5 rom1 4 rom0 3 1 2 1 1 ram1 0 ram0 ims rom1 0 0 rom0 0 1 other than above 32 kb 64 kb setting prohibited internal rom capacity selection address: 0fffch after reset: deh r/w ram1 0 1 ram0 1 0 other than above 768 bytes 1.5 kb setting prohibited peripheral ram capacity selection
m pd78f4046 17 data sheet u11447ej2v0ds00 7. flash memory programming the flash memory can be written with the m pd78f4046 mounted on the target board (on-board write). writing is performed with the dedicated flash programmer flashpro ii (part number: fl-pr2) and flashpro iii (part number: fl-pr3, pg-fp3)) connected to the host machine and the target system. remark flashpro ii and iii are products of naito densei machida mfg. co., ltd.. 7.1 selecting communication mode writing to flash memory is performed using the flashpro ii and iii via a serial communication mode. select a serial communication mode from those listed in table 7-1. the selection of the communication mode is made by using the format shown in figure 7-1. each communication mode is selected by the number of v pp pulses shown in table 7-1. table 7-1. list of communication modes communication mode number of channels pins used number of v pp pulses 3-wire serial i/o 2 p34/asck/sck1 0 p33/txd/so1 p32/rxd/si1 p37/asck2/sck2 1 p36/txd2/so2 p35/rxd2/si2 uart 2 p33/txd/so1 8 p32/rxd/si1 p36/txd2/so2 9 p35/rxd2/si2 figure 7-1. format of communication mode selection 10 v mode/v pp v dd v ss v dd v ss reset
m pd78f4046 18 data sheet u11447ej2v0ds00 7.2 function of flash memory programming operations such as writing to flash memory are performed by various command/data transmission and reception operations according to the selected communication mode. table 7-2 shows the major functions of flash memory programming. table 7-2. major functions of flash memory programming function description batch erase erases the entire memory contents. block erase erases the contents of the specified memory block, with one memory block consisting of 16 kb. batch blank check checks the erasure status of the entire memory. block blank check checks the erasure status of the specified block. data write writes to the flash memory based on the write start address and the amount of data to be written (number of bytes). batch verify compares the entire memory contents with the input data. block verify compares the contents of the specified memory block with the input data. 7.3 connection of flashpro ii and flashpro iii the connection of the dedicated flash programmer and the m pd78f4046 differs according to the communication mode (3-wire serial i/o or uart). the connection for each communication mode is shown in figures 7-2 and 7-3. figure 7-2. connection of flashpro ii and flashpro iii in 3-wire serial i/o mode figure 7-3. connection of flashpro ii and flashpro iii in uart mode v pp v dd reset sck1 or sck2 si1 or si2 so1 or so2 v ss flashpro ii, flashpro iii pd78f4046 m v pp v dd reset rxd or rxd2 txd or txd2 v ss flashpro ii, flashpro iii pd78f4046 m
m pd78f4046 19 data sheet u11447ej2v0ds00 7.4 cautions when writing to flash memory for writing data to the flash memory of the m pd78f4046, use the prewrite and ecc functions. moreover, set the flash programmer as follows when writing to flash memory using these functions. either 1-bit or 8-bit memory manipulation instructions can be used to make these settings. (1) using prewrite function to improve flash memory rewrite characteristics, prewriting is necessary before erasing. prewriting involves writing 00h to all the data. this is performed to delete the bits that are already 1 in the data (erasure state), and to prevent further erasure stress. (2) using ecc function when writing to the m pd78f4046 and shipping it as a product, ecc data needs to be written in the ecc data area of flash memory. by writing ecc data and setting the ecc function, data writing can be performed correctly. <1> creating ecc data convert the ex file to an ecc-attached hex file using the ecc generator included in the assembly package (ver. 1.20 or later for pc). download this ecc-attached hex file to the flash programmer, and then write. [ecc data creating method] ? prepare the hex file created by the object converter of the assembly package. ? convert it to the program data + hex file using the ecc generator (eccgen.exe) included in the assembly package. example convert the file file.hex to file_ec.hex. ec file.hex-ofile_ec.hex -a0ffffh, 10000h, 14000h, 14004h <2> flash programmer (flashpro ii, flashpro iii) setting and writing prewriting and ecc writing are performed by flashpro ii and flashpro iii. the setting method when using an earlier version than flashpro ii ver. 2.50 is described below. remark if using flashpro ii ver. 2.50 or later or flashpro iii (pg-fp3 (ver. 3.040 or later, products of nec corporation)), setting is not necessary. setting is performed automatically by reading parameter files.
m pd78f4046 20 data sheet u11447ej2v0ds00 [when earlier version than flashpro ii ver. 2.50 is used] a. connect the pc and fl-pr2, then start up the control software flashpro.exex. b. press the ctrl + grph (art) + p keys at the same time. c. check the check box of pre-write set. ? prewrite setting d. press the ok button. e. select setting. f. select option. g. check the ecc code area in the menu window. h. input 14004 to ecc end address ecc write setting i. press the ok button. j. press the type button. k. input 14004 to end address l. press the ok button [writing method] a. download the ecc-attached hex file to the flash programmer. b. set to chip mode and write using the e.p.v button. do not use the program command, since this will disable writing to ecc.
m pd78f4046 21 data sheet u11447ej2v0ds00 8. electrical specifications absolute maximum ratings (t a = 25?c) parameter symbol conditions ratings unit supply voltage v dd C0.5 to +7.0 v av dd C0.5 to v dd + 0.5 v av ss C0.5 to +0.5 v input voltage v i1 note 1 C0.5 to v dd + 0.5 7.0 v v i2 test/v pp pin in the programming mode C0.5 to +11.0 v output voltage v o C0.5 to v dd + 0.5 v output current, low i ol all output pins 15 ma total of all output pins 150 ma output current, high i oh all output pins C10 ma total of all output pins C100 ma analog input voltage v ian note 2 av dd > v dd C0.5 to v dd + 0.5 v v dd 3 av dd C0.5 to av dd + 0.5 a/d converter reference av ref av dd > v dd C0.5 to v dd + 0.5 v input voltage v dd 3 av dd C0.5 to av dd + 0.5 operating ambient t a C10 to +70 ?c temperature storage temperature t stg C40 to +125 ?c notes 1. pins other than the pins specified in note 2. 2. pins p70/ani0 to p77/ani7, p80/ani8 to p87/ani15 caution product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameter. that is, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions that the absolute maximum ratings are not exceeded. recommended operating conditions oscillation frequency t a v dd 8 mhz f xx 32 mhz C10 to +70?c 4.5 to 5.5 v capacitance (t a = 25?c, v ss = v dd = 0 v) parameter symbol conditions min. typ. max. unit input capacitance c i f = 1 mhz 10 pf output capacitance c o unmeasured pins returned to 0 v. 10 pf i/o capacitance c io 10 pf
m pd78f4046 22 data sheet u11447ej2v0ds00 flash memory specifications (t a = +10 to +40?c (rewriting), t a = C10 to +70?c (other than rewriting)) parameter symbol conditions min. typ. max. unit v dd supply voltage v dd 4.5 5.5 v v pp supply voltage v pp v pp high-voltage detection 9.7 10.0 10.3 v number of rewrites note 10 times note if the number of flash memory rewrites exceeds 10, operation is not guaranteed. oscillator characteristics (t a = C10 to +70?c, v dd = 4.5 to 5.5 v, v ss = 0 v) resonator recommended circuit parameter min. max. unit ceramic resonator or oscillation frequency (f xx ) 8 32 mhz crystal resonator external clock x1 input frequency (f x ) 8 32 mhz x1 input rise/fall time 0 5 ns x1 input high-/low-level 20 105 ns width note when the extc bit of the oscillation stabilization time specification register (osts) = 0. input the reverse phase clock of pin x1 to pin x2 when the extc bit = 1. caution when using the system clock oscillator, wire as follows in the area enclosed by the broken lines in the above figures to avoid an adverse effect from wiring capacitance. ? keep the wiring length as short as possible. ? do not cross the wiring with the other signal lines. do not route the wiring near a signal line through which a high fluctuating current flows. ? always make the ground point of the oscillator capacitor the same potential as v ss . do not ground the capacitor to a ground pattern through which a high current flows. ? do not fetch signals from the oscillator. remark for the resonator selection and oscillator constant, customers are requested to either evaluate the oscillation themselves or apply to the resonator manufacturer for evaluation. c1 c2 v ss x1 x2 x1 x2 open note hcmos inverter
m pd78f4046 23 data sheet u11447ej2v0ds00 dc characteristics (t a = C10 to +70?c, v dd = 4.5 to 5.5 v, v ss = 0 v) parameter symbol conditions min. typ. max. unit input voltage, low v il 0 0.8 v input voltage, high v ih1 note 1 2.2 v dd v v ih2 note 2 0.8v dd v dd output voltage, low v ol i ol = 2.0 ma 0.45 v output voltage, high v oh i oh = C400 m av dd C 1.0 v input leakage current i li note 3 0 v v i v dd 10 m a analog pin input leakage current i lian note 4 0 v v i av dd 1 m a output leakage current i lo 0 v v o v dd 10 m a v dd supply current i dd1 operating mode (f xx = 32 mhz) 50 80 ma i dd2 halt mode (f xx = 32 mhz) 30 60 ma i dd3 idle mode (f xx = 32 mhz) 10 20 ma data retention voltage v dddr stop mode 2.5 v data retention current i dddr stop mode v dddr = 2.5 v 215 m a v dddr = 5 v 10% 15 50 m a pull-up resistor r l 15 40 80 k w notes 1. pins other than the pins specified in note 2 2. p20/nmi, p21/intp0/to00, p22/intp1/to01, p23/intp2/to02, p24/intp3/to03, p25/intp4, p26/ intp5/ti2, p27/intp6/ti3, p34/asck/sck1, p37/asck2/sck2, x1, x2, reset 3. input and i/o pins (except x1 and x2, and p70/ani0 to p77/ani7, p80/ani8 to p87/ani15 used as analog inputs) 4. pins p70/ani0 to p77/ani7, p80/ani8 to p87/ani15 (pins used as analog inputs, and only during a non-sampling operation)
m pd78f4046 24 data sheet u11447ej2v0ds00 ac characteristics (t a = C10 to +70?c, v dd = 4.5 to 5.5 v, v ss = 0 v) read/write operation parameter symbol expression min. max. unit system clock cycle time t cyk 62.5 250 ns address setup time (to astb )t sast (0.5 + a) t C 20 11.2 ns address hold time (from astb )t hsta 0.5t C 20 11.2 ns astb high-level width t wsth (0.5 + a) t C 17 14.2 ns rd delay time from address t dar (1 + a) t C 15 47.5 ns address float time from rd t fra 0ns data input time from address t daid (2.5 + a + n) t C 56 100.2 ns data input time from rd t drid (1.5 + n) t C 48 45.7 ns delay time from astb to rd t dstr 0.5t C 16 15.3 ns data hold time (from rd - )t hrid 0ns address active time from rd - t dra 0.5t C 14 17.2 ns rd low-level width t wrl (1.5 + n) t C 30 63.7 ns delay time from address to lwr, hwr t daw (1 + a) t C 15 47.5 ns data output time from lwr, hwr t dwod 15 ns delay time from astb to lwr, hwr t dstw 0.5t C 16 15.3 ns data setup time (to lwr, hwr - )t sodw (1.5 + n) t C 25 68.7 ns data hold time (from lwr, hwr - )t hwod 0.5t C 14 17.2 ns delay time from lwr, hwr - to astb - t dwst 1.5t C 15 78.8 ns lwr, hwr low-level width t wwl (1.5 + n) t C 36 57.7 ns wait input time from address t dawt (2 + a) t C 50 75 ns wait input time from astb t dstwt 1.5t C 40 53.7 ns wait hold time from astb t hstwt (1.5 + n) t + 5 98.8 ns delay time from astb to wait - t dstwth (2.5 + n) t C 40 116.2 note ns wait input time from rd t drwt t C 40 22.5 ns wait hold time from rd t hrwt (1 + n) t + 5 67.5 ns delay time from rd to wait - t drwth (1 + n) t C 40 85 note ns wait input time from lwr, hwr t dwwt t C 40 22.5 ns wait hold time from lwr, hwr t hwwt (1 + n) t + 5 67.5 ns delay time from lwr, hwr to wait - t dwwth (1 + n) t C 40 85 note ns note specification when an external wait is inserted remarks 1. t = t cyk = 1/f clk (f clk is internal system clock frequency) 2. a = 1 when an address wait is inserted, otherwise 0. 3. n indicates the number of the wait cycles as specified by the external wait pin (wait) or programmable wait control registers 1, 2 (pwc1, pwc2). (n 3 0. n 3 1 for t dstwth , t drwth , t dwwth ). 4. calculate values in the expression column with the system clock cycle time to be used because these values depend on the system clock cycle time (t cyk = t). the values in the above expression column are calculated based on t = 62.5 ns.
m pd78f4046 25 data sheet u11447ej2v0ds00 serial operation (t a = C10 to +70?c, v dd = 4.5 to 5.5 v, v ss = 0 v) parameter symbol conditions min. max. unit serial clock cycle time t cysk sck1, sck2 output brg t sft ns sck1, sck2 input external clock 500 ns serial clock low-level width t wskl sck1, sck2 output brg 0.5t sft C40 ns sck1, sck2 input external clock 210 ns serial clock high-level width t wskh sck1, sck2 output brg 0.5t sft C40 ns sck1, sck2 input external clock 210 ns si1, si2 setup time t sssk 80 ns (to sck1, sck2 - ) si1, si2 hold time t hssk 80 ns (from sck1, sck2 - ) delay time from sck1, sck2 t dsbsk r = 1 k w , c = 100 pf 0 150 ns to so1, so2 output remarks 1. t sft is a value set by software. the minimum value is t cyk 8. 2. t cyk = 1/f clk (f clk is internal system clock frequency) other operations (t a = C10 to +70?c, v dd = 4.5 to 5.5 v, v ss = 0 v) parameter symbol conditions min. max. unit nmi high-/low-level width t wnih , t wnil 10 m s intp0 to intp6 high-/low-level width t with , t witl 4t cysmp ti2, ti3 high-/low-level width t wtih , t wtil 4t cysmp reset high-/low-level width t wrsh , t wrsl 10 m s remarks 1. t cysmp is a sampling clock set by software in the noise protection control register (npc). when nin = 0, t cysmp = t cyk when nin = 1, t cysmp = t cyk 4 2. t cyk = 1/f clk (f clk is internal system clock frequency) 3. nin: bit n of npc (n = 0 to 6) ac timing test points v dd 0 v 0.8v dd or 2.2 v 0.8 v 0.8v dd or 2.2 v 0.8 v test points
m pd78f4046 26 data sheet u11447ej2v0ds00 ad converter characteristics (t a = C10 to +70?c, v dd = 4.5 to 5.5 v, v ss = av ss = 0 v, v dd C 0.5 v av dd v dd ) parameter symbol conditions min. typ. max. unit resolution 10 bit overall error note 1 4.5 v av ref av dd 0.5 %fsr note 2 3.4 v av ref < 4.5 v 0.7 %fsr note 2 quantization error 1/2 lsb conversion time t conv 80 ns t cyk 250 ns 169 t cyk 62.5 ns t cyk < 80 ns 208 t cyk sampling time t samp 80 ns t cyk 250 ns 20 t cyk 62.5 ns t cyk < 80 ns 24 t cyk zero-scale error note 1 4.5 v av ref av dd 1.5 3.5 lsb 3.4 v av ref < 4.5 v 1.5 4.5 lsb full-scale error note 1 4.5 v av ref av dd 1.5 3.5 lsb 3.4 v av ref < 4.5 v 1.5 4.5 lsb integral linearity error note 1 4.5 v av ref av dd 1.5 2.5 lsb 3.4 v av ref < 4.5 v 1.5 4.5 lsb analog input voltage v ian C0.3 av ref + 0.3 v a/d converter reference input av ref 3.4 av dd v voltage av ref current ai ref 1.0 3.0 ma av dd supply current ai dd 2.0 6.0 ma a/d converter data retention ai dddr stop av dddr = 2.5 v 2 10 m a current mode av dddr = 5 v 10% 10 50 m a notes 1. excludes quantization error. 2. indicated as a ratio (%fsr) to the full-scale value. remark t cyk = 1/f clk (f clk is the internal system clock frequency)
m pd78f4046 27 data sheet u11447ej2v0ds00 read operation (8 bits) (clk) ad8 to ad15 (output) ad0 to ad7 (i/o) astb (output) rd (output) wait (input) higher address higher address lower address (output) data (input) lower address (output) t cyk t wsth t hsta t dstr t dar t wrl t dstwth t hstwt t dstwt t drwt t dawt t hrwt t drwth t drid t dra t fra t hrid t sast t daid hi-z hi-z hi-z hi-z
m pd78f4046 28 data sheet u11447ej2v0ds00 write operation (8 bits) (clk) ad8 to ad15 (output) ad0 to ad7 (output) astb (output) lwr (output) wait (input) t cyk t dstwth t hstwt t dstwt t dwwt t dawt t hwwt t dwwth t dstw t hsta t wsth t sast t hwod t dwst t dwod t sodw t daw t wwl higher address higher address lower address (output) undefined data (output) lower address (output)
m pd78f4046 29 data sheet u11447ej2v0ds00 read operation (16 bits) (clk) t cyk address (output) data (input) address (output) t wsth t hsta t dstr t dar t wrl t dstwth t hstwt t dstwt t drwt t dawt t hrwt t drwth t drid t dra t fra t hrid t sast t daid hi-z hi-z hi-z hi-z ad8 to ad15 ad0 to ad7 (i/o) astb (output) rd (output) wait (input)
m pd78f4046 30 data sheet u11447ej2v0ds00 write operation (16 bits) (clk) ad8 to ad15 ad0 to ad7 (output) astb (output) hwr, lwr (output) wait (input) t cyk t dstwth t hstwt t dstwt t dwwt t dawt t hwwt t dwwth t dstw t hsta t wsth t sast t hwod t dwst t dwod t sodw t daw t wwl address (output) data (output) undefined address (output)
m pd78f4046 31 data sheet u11447ej2v0ds00 serial operation interrupt input timing reset input timing timer input timing sck1, sck2 so1, so2 si1, si2 t cysk t wskl t dsbsk t sssk t hssk t wskh t wnih t wnil 0.8v dd 0.8 v t with t witl 0.8v dd 0.8 v nmi intp0 to intp6 t wrsh t wrsl 0.8v dd 0.8 v reset t wtih t wtil 0.8v dd 0.8 v ti2, ti3
m pd78f4046 32 data sheet u11447ej2v0ds00 9. package drawing 80-pin plastic qfp (14x14) note each lead centerline is located within 0.13 mm of its true position (t.p.) at maximum material condition. item millimeters a b d g 17.2 0.4 14.0 0.2 0.13 0.825 i 17.2 0.4 j c 14.0 0.2 h 0.30 0.10 0.65 (t.p.) k 1.6 0.2 l 0.8 0.2 f 0.825 s80gc-65-3b9-6 n p q 0.10 2.7 0.1 0.1 0.1 r s 5 5 3.0 max. m 0.15 + 0.10 - 0.05 60 61 40 80 1 21 20 41 s s n j detail of lead end c d a b r k m l p i s q g f m h
m pd78f4046 33 data sheet u11447ej2v0ds00 10. recommended soldering conditions the m pd78f4046 should be soldered and mounted under the following recommended conditions. for the details of the recommended soldering conditions, refer to the document semiconductor device mounting technology manual (c10535e) . for soldering methods and conditions other than those recommended below, contact your nec representative. table 10-1. surface mounting type soldering conditions m pd78f4046gc-3b9: 80-pin plastic qfp (14 14 mm) soldering method soldering conditions recommended condition symbol infrared reflow package peak temperature: 235 c, time: 30 seconds max. (at 210 c or ir35-207-2 higher), count: twice or less, exposure limit: 7 days note (after 7 days, prebake at 125 c for 20 hours) vps package peak temperature: 215 c, time: 40 seconds max. (at 200 c or vp15-207-2 higher), count: twice or less, exposure limit: 7 days note (after 7 days, prebake at 125 c for 20 hours) wave soldering solder bath temperature: 260 c max., time: 10 seconds max., count: ws60-207-1 once, preheating temperature: 120 c max. (package surface temperature), exposure limit: 7 days note (after 7 days, prebake at 125 c for 20 hours) partial heating pin temperature: 300 c max., time: 3 seconds max. (per pin row) C note after opening the dry pack, store it at 25 c or less and 65% rh or less for the allowable storage period. caution do not use different soldering methods together (except for partial heating).
m pd78f4046 34 data sheet u11447ej2v0ds00 appendix a. development tools the following development tools are available for system development using the m pd78f4046. refer to (5) cautions on using development tools. (1) language processing software ra78k4 assembler package common to 78k/iv series cc78k4 c compiler package common to 78k/iv series df784046 device file for m pd784046 subseries cc78k4-l c compiler library source file common to 78k/iv series (2) flash memory writing tools flashpro ii (model fl-pr2), dedicated flash programmer for microcontrollers incorporating flash memory flashpro iii (model fl-pr3, pg-fp3) fa-80gc adapter for flash memory programming (3) debugging tools ? when ie-78k4-ns in-circuit emulator is used ie-78k4-ns in-circuit emulator common to 78k/iv series ie-70000-mc-ps-b power supply unit for ie-78k4-ns ie-70000-98-if-c interface adapter necessary when a pc-9800 series pc (except notebook pc) is used as the host machine (c bus supported) ie-70000-cd-if pc card and interface cable necessary when a pc-9800 series notebook pc is used as the host machine (pcmcia socket supported) ie-70000-pc-if-c interface adapter necessary when an ibm pc/at tm -compatible is used as the host machine (isa bus supported) ie-784046-ns-em1 emulation board for emulating m pd784046 subseries np-80gc emulation probe for 80-pin plastic qfp (gc-3b9 type) ev-9200gc-80 socket to be mounted on the board of the target system for 80-pin plastic qfp (gc-3b9 type) id78k4-ns integrated debugger for ie-78k4-ns sm78k4 system simulator common to 78k/iv series df784046 device file for the m pd784046 subseries
m pd78f4046 35 data sheet u11447ej2v0ds00 ? when using the ie-784000-r in-circuit emulator ie-784000-r in-circuit emulator common to 78k/iv series ie-70000-98-if-c interface adapter necessary when a pc-9800 series pc (except notebook pc) is used as the host machine (c bus supported) ie-70000-pc-if-c interface adapter necessary when an ibm pc/at-compatible is used as the host machine (isa bus supported) ie-70000-pci-if interface adapter necessary when pc that incorporates pci bus is used as host machine ie-78000-r-sv3 interface adapter and cable necessary when an ews is used as the host machine ie-784000-r-em emulation board common to 78k/iv series ie-784046-ns-em1 emulation board for emulating m pd784046 subseries ie-784046-r-em1 ie-78k4-r-ex2 emulation probe conversion board necessary when the ie-784046-ns-em1 is used in the ie-784000-r. not necessary when the ie-784046-r-em1 is used. ep-78230gc-r emulation probe for 80-pin plastic qfp (gc-3b9 type) ev-9200gc-80 socket to be mounted on the board of the target system made for the 80-pin plastic qfp (gc-3b9 type) id78k4 integrated debugger for ie-784000-r sm78k4 system simulator common to 78k/iv series df784046 device file for m pd784046 subseries (4) real-time os rx78k/iv real-time os for 78k/iv series mx78k4 os for 78k/iv series
m pd78f4046 36 data sheet u11447ej2v0ds00 (5) cautions on using development tools ? the id78k4-ns, id78k4, and sm78k4 are used in combination with the df784046. ? the cc78k4 and rx78k/iv are used in combination with the ra78k4 and df784046. ? fl-pr2, fl-pr3, fa-80gc, and np-80gc are products of naito densei machida mfg. co., ltd. (tel: +81- 44-822-3813). ? the host machine and os suitable for each software are as follows: host machine [os] pc ews pc-9800 series [windows tm ] hp9000 series 700 tm [hp-ux tm ] ibm pc/at-compatible sparcstation tm [sunos tm , solaris tm ] software [japanese/english windows] news tm (risc) [news-os tm ] ra78k4 ? note ? cc78k4 ? note ? id78k4-ns ? C id78k4 ?? sm78k4 ? C rx78k/iv ? note ? mx78k4 ? note ? note dos-based software
m pd78f4046 37 data sheet u11447ej2v0ds00 appendix b. related documents documents related to devices document document no. japanese english m pd784044, 784046 data sheet u10951j u10951e m pd78f4046 data sheet u11447j this manual m pd784046 subseries users manual - hardware u11515j u11515e m pd784046 subseries special function register table u10986j C 78k/iv series users manual - instruction u10905j u10905e 78k/iv series instruction list u10594j C 78k/iv series instruction set u10595j C 78k/iv series application note - software basics u10095j u10095e documents related to development tools (users manuals) document document no. japanese english ra78k4 assembler package operation u11334j u11334e language u11162j u11162e ra78k4 structured assembler preprocessor u11743j u11743e cc78k4 c compiler operation u11572j u11572e language u11571j u11571e ie-78k4-ns u13356j u13356e ie-784000-r u12903j u12903e ie-784046-ns-em1 u13744j u13744e ie-784046-r-em1 u11677j u11677e ep-78230 eeu-985 eeu-1515 sm78k4 system simulator windows based reference u10093j u10093e sm78k series system simulator external part user open u10092j u10092e interface specifications id78k4-ns integrated debugger pc based reference u12796j u12796e id78k4 integrated debugger windows based reference u10440j u10440e id78k4 integrated debugger reference u11960j u11960e hp-ux, sunos, news-os based caution the related documents listed above are subject to change without notice. be sure to use the latest version of each document for designing.
m pd78f4046 38 data sheet u11447ej2v0ds00 documents related to embedded software (users manuals) document document no. japanese english 78k/iv series real-time os fundamentals u10603j u10603e installation u10604j u10604e debugger u10364j C 78k/iv series os mx78k4 fundamental u11779j C other documents document document no. japanese english semiconductor selection guide products & packages (cd-rom) x13769x semiconductor device mounting technology manual c10535j c10535e quality grades on nec semiconductor devices c11531j c11531e nec semiconductor device reliability/quality control system c10983j c10983e guide to prevent damage for semiconductor devices by c11892j c11892e electrostatic discharge (esd) guide to microcomputer-related products by third parties u11416j C caution the related documents listed above are subject to change without notice. be sure to use the latest version of each document for designing.
m pd78f4046 39 data sheet u11447ej2v0ds00 [memo]
m pd78f4046 40 data sheet u11447ej2v0ds00 [memo]
m pd78f4046 41 data sheet u11447ej2v0ds00 [memo]
m pd78f4046 42 data sheet u11447ej2v0ds00 notes for cmos devices 1 precaution against esd for semiconductors note: strong electric field, when exposed to a mos device, can cause destruction of the gate oxide and ultimately degrade the device operation. steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. environmental control must be adequate. when it is dry, humidifier should be used. it is recommended to avoid using insulators that easily build static electricity. semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. all test and measurement tools including work bench and floor should be grounded. the operator should be grounded using wrist strap. semiconductor devices must not be touched with bare hands. similar precautions need to be taken for pw boards with semiconductor devices on it. 2 handling of unused input pins for cmos note: no connection for cmos device inputs can be cause of malfunction. if no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. cmos devices behave differently than bipolar or nmos devices. input levels of cmos devices must be fixed high or low by using a pull-up or pull-down circuitry. each unused pin should be connected to v dd or gnd with a resistor, if it is considered to have a possibility of being an output pin. all handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 status before initialization of mos devices note: power-on does not necessarily define initial status of mos device. production process of mos does not define the initial operation status of the device. immediately after the power source is turned on, the devices with reset function have not yet been initialized. hence, power-on does not guarantee out-pin levels, i/o settings or contents of registers. device is not initialized until the reset signal is received. reset operation must be executed immediately after power-on for devices having reset function. windows is either a registered trademark or a trademark of microsoft corporation in the united states and/or other countries. pc/at is a trademark of international business machines corporation. hp9000 series 700 and hp-ux are trademarks of hewlett-packard company. sparcstation is a trademark of sparc international, inc. solaris and sunos are trademarks of sun microsystems inc. news and news-os are trademarks of sony corporation.
m pd78f4046 43 data sheet u11447ej2v0ds00 regional information some information contained in this document may vary from country to country. before using any nec product in your application, piease contact the nec office in your country to obtain a list of authorized representatives and distributors. they will verify: device availability ordering information product release schedule availability of related technical literature development environment specifications (for example, specifications for third-party tools and components, host computers, power plugs, ac supply voltages, and so forth) network requirements in addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary from country to country. nec electronics inc. (u.s.) santa clara, california tel: 408-588-6000 800-366-9782 fax: 408-588-6130 800-729-9288 nec electronics (germany) gmbh duesseldorf, germany tel: 0211-65 03 02 fax: 0211-65 03 490 nec electronics (uk) ltd. milton keynes, uk tel: 01908-691-133 fax: 01908-670-290 nec electronics italiana s.r.l. milano, italy tel: 02-66 75 41 fax: 02-66 75 42 99 nec electronics (germany) gmbh benelux office eindhoven, the netherlands tel: 040-2445845 fax: 040-2444580 nec electronics (france) s.a. velizy-villacoublay, france tel: 01-30-67 58 00 fax: 01-30-67 58 99 nec electronics (france) s.a. madrid office madrid, spain tel: 91-504-2787 fax: 91-504-2860 nec electronics (germany) gmbh scandinavia office taeby, sweden tel: 08-63 80 820 fax: 08-63 80 388 nec electronics hong kong ltd. hong kong tel: 2886-9318 fax: 2886-9022/9044 nec electronics hong kong ltd. seoul branch seoul, korea tel: 02-528-0303 fax: 02-528-4411 nec electronics singapore pte. ltd. united square, singapore tel: 65-253-8311 fax: 65-250-3583 nec electronics taiwan ltd. taipei, taiwan tel: 02-2719-2377 fax: 02-2719-5951 nec do brasil s.a. electron devices division guarulhos-sp brasil tel: 55-11-6462-6810 fax: 55-11-6462-6829 j00.7
m pd78f4046 44 the related documents indicated in this publication may include preliminary versions. however, preliminary versions are not marked as such. m8e 00. 4 the information in this document is current as of july, 2000. the information is subject to change without notice. for actual design-in, refer to the latest publications of nec's data sheets or data books, etc., for the most up-to-date specifications of nec semiconductor products. not all products and/or types are available in every country. please check with an nec sales representative for availability and additional information. no part of this document may be copied or reproduced in any form or by any means without prior written consent of nec. nec assumes no responsibility for any errors that may appear in this document. nec does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from the use of nec semiconductor products listed in this document or any other liability arising from the use of such products. no license, express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of nec or others. descriptions of circuits, software and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. the incorporation of these circuits, software and information in the design of customer's equipment shall be done under the full responsibility of customer. nec assumes no responsibility for any losses incurred by customers or third parties arising from the use of these circuits, software and information. while nec endeavours to enhance the quality, reliability and safety of nec semiconductor products, customers agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. to minimize risks of damage to property or injury (including death) to persons arising from defects in nec semiconductor products, customers must incorporate sufficient safety measures in their design, such as redundancy, fire-containment, and anti-failure features. nec semiconductor products are classified into the following three quality grades: "standard", "special" and "specific". the "specific" quality grade applies only to semiconductor products developed based on a customer-designated "quality assurance program" for a specific application. the recommended applications of a semiconductor product depend on its quality grade, as indicated below. customers must check the quality grade of each semiconductor product before using it in a particular application. "standard": computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots "special": transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) "specific": aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems and medical equipment for life support, etc. the quality grade of nec semiconductor products is "standard" unless otherwise expressly specified in nec's data sheets or data books, etc. if customers wish to use nec semiconductor products in applications not intended by nec, they must contact an nec sales representative in advance to determine nec's willingness to support a given application. (note) (1) "nec" as used in this statement means nec corporation and also includes its majority-owned subsidiaries. (2) "nec semiconductor products" means any semiconductor product developed or manufactured by or for nec (as defined above).

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